DS3803 1024k flexible nv sram simm DS3803 042398 1/10 features ? flexibly organized as 32k x 32, 64k x 16 or 128k x 8 bits ? 10 years minimum data retention in the absence of external power ? nonvolatile circuitry transparent to and independent from host system ? automatic write protection circuitry safeguards against data loss ? separate control and data signals for each sram allow byte, word or doubleword access ? fast access time of 70 ns ? full v cc 10% operating range ? employs popular jedec standard 72position simm connector ? extremely thin design built using tsoppackage ic components pin description a0 a14 address inputs d0a d7a data inputs/outputs, byte a d0b d7b data inputs/outputs, byte b d0c d7c data inputs/outputs, byte c d0d d7d data inputs/outputs, byte d cea ced chip enable inputs wea wed write enable inputs oea oed output enable inputs vcc +5v power supply gnd ground nc no connect pin assignment 256k sram 72 1 DS3803 72pin simm 256k sram 256k sram 256k sram description the DS3803 is a selfcontained 1,048,576bit, nonvol- atile static ram which can be flexibly organized as 32k x 32, 64k x 16 or 128k x 8. built using four 32k x 8 srams, four nonvolatile control ics and four lithium bat- teries, this nonvolatile memory contains all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of power for more than 10 years. the DS3803 employs the popular jedec stan- dard 72position simm connection scheme and requires no additional circuitry.
DS3803 042398 2/10 read mode the DS3803 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 15 address inputs (a 0 a 14 ) defines which byte of data is to be accessed from the selected srams. valid data will be available to the data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later occurring signal and the limiting parameter is either t co for ce or t oe for oe rather than t acc . write mode the DS3803 executes a write cycle whenever both we and ce signals are in the active (low) state after address inputs are stable. the later occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inac- tive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled (ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the DS3803 provides full functional capability for v cc greater than 4.5 volts and write protects by 4.25 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static ram constantly monitors v cc . should the supply voltage decay, the nv sram automatically write protects itself, all inputs become dont care, and all outputs become high impedance. as v cc falls below approximately 3.0 volts, power switching circuits connect the lithium energy sources to the rams to retain data. during pow- erup, when v cc rises above approximately 3.0 volts, the power switching circuits connect external v cc to the rams and disconnects the lithium energy source. nor- mal ram operation can resume after v cc exceeds 4.5 volts. the DS3803 checks battery status to warn of potential data loss. each time that v cc power is restored to the DS3803, the battery voltages are checked with preci- sion comparators. if both batteries providing backup power to a particular sram are less than 2.0 volts, the second memory access to that sram is inhibited. bat- tery status for each sram can, therefore, be deter- mined by a threestep process. first, a read cycle is performed to any location within that sram, in order to save the contents of that location. a subsequent write cycle can then be executed to the same memory loca- tion, altering data. if a subsequent read cycle fails to verify the written data, then battery voltage for that sram is less than 2.0v and data is in danger of being lost. the DS3803 also provides battery redundancy. in many applications data integrity is paramount. the DS3803 provides two batteries for each sram and an internal isolation switch to select between them. during battery backup, the battery with the highest voltage is selected for use. if one battery fails, the other automati- cally takes over. the switch between batteries is trans- parent to the user.
DS3803 042398 3/10 pin description table 1 pin signal name pin signal name pin signal name pin signal name pin signal name 1 v cc 16 d2b 31 d5c 46 nc 61 a9 2 d0a 17 d3b 32 d6c 47 ced 62 a10 3 d1a 18 d4b 33 d7c 48 oed 63 a11 4 d2a 19 d5b 34 nc 49 wed 64 a12 5 d3a 20 d6b 35 cec 50 gnd 65 a13 6 d4a 21 d7b 36 oec 51 v cc 66 a14 7 d5a 22 nc 37 wec 52 a0 67 nc 8 d6a 23 ceb 38 d0d 53 a1 68 nc 9 d7a 24 ceb 39 d1d 54 a2 69 nc 10 nc 25 web 40 d2d 55 a3 70 nc 11 cea 26 d0c 41 d3d 56 a4 71 nc 12 oea 27 d1c 42 d4d 57 a5 72 gnd 13 wea 28 d2c 43 d5d 58 a6 14 d0b 29 d3c 44 d6d 59 a7 15 d1b 30 d4c 45 d7d 60 a8
DS3803 042398 4/10 block diagram figure 1 a0a14 v cc 32k x 8 sram a0a14 wea oea wea cea we oe ce d0 d7 v cco v cci ds1210 ceo cei bat v bat1 v bat2 a0a14 v cc 32k x 8 sram we oe ce d0 d7 ds1210 ceo cei bat v bat1 a0a14 v cc 32k x 8 sram we oe ce d0 d7 ds1210 ceo cei bat v bat1 a0a14 v cc 32k x 8 sram we oe ce d0 d7 ds1210 ceo cei bat v bat1 oeb web ceb d0ad7a d0ad7b d0ad7c d0ad7d oec wec cec oed wed ced v bat2 v bat2 v bat2 v cco v cci v cco v cci v cco v cci
DS3803 042398 5/10 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 40 c to +85 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a = 0 c to 70 c) parameter symbol min typ max units notes power supply voltage v cc 4.5 5.0 5.5 v logic 1 input voltage v ih 2.2 v cc +0.3 v logic 0 input voltage v il 0.3 +0.8 v dc electrical characteristics (t a = 0 c to 70 c; v cc = 5v 10%) parameter symbol test condition min typ max units input leakage current i il 0v v in v cc 4 +4 m a output leakage current i lo 0v v in v cc , all ce = v ih 1 +1 m a operating current i cco min cycle, duty=100% all ce = v il , i i/o = 0, v in = v ih or v il 300 ma standby current i ccs all ce = v ih 20 ma output high current i oh v oh = 2.4v 1.0 ma output low current i ol v ol = 0.4v 2.1 ma capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 8 pf output capacitance c i/o 10 pf
DS3803 042398 6/10 ac electrical characteristics (t a = 0 c to 70 c; v cc = 5v 10%) parameter symbol min typ max units notes read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 deselection to output high z t od 25 ns 5 output hold after address change t oh 5 ns write cycle time t wc 70 ns write pulse width t wp 55 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 15 ns 11 12 we active to output high z t odw 25 ns 5 we inactive to output active t oew 5 ns 5 data setup time t ds 30 ns 4 data hold time t dh1 t dh2 0 10 ns 11 12 timing diagram: read cycle t rc t acc v ih v il v ih v il v ih v il t oh v ih t od t od v ih v oh v ol v oh v ol t coe t coe output data valid d out oe addresses v ih v ih t oe v il v il ce t co see note 1
DS3803 042398 7/10 timing diagram: write cycle 1 (we controlled) t wc v ih v il v ih v il v ih v il addresses t aw data in stable high impedance v il v il v il v il v ih v ih t wp t wr1 t odw t oew t ds t dh1 v ih v il v ih v il ce we d out d in see notes 2, 3, 4, 6, 7, 8 and 11 timing diagram: write cycle 2 (ce controlled) t wc v il v ih v il v ih v il v ih addresses ce we d out d in data in stable t aw t wp t wr2 v ih v il v il v il v ih v ih v il v il t coe t odw t ds t dh2 v il v ih v il v ih see notes 2, 3, 4, 6, 7, 8 and 12
DS3803 042398 8/10 timing diagram: powerdown and powerup v cc 2.7v t f t pd t r t rec backup current supplied from lithium battery ce , we v tp see note 10 t dr slews with v cc t pu v ih powerdown/powerup timing parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 m s v cc slew from v tp to 0v t f 300 m s v cc slew from 0v to v tp t r 300 m s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a = 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is high throughout read cycle. 2. oe = v ih or v il . if oe = vih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested.
DS3803 042398 9/10 6. if the ce low transition occurs simultaneously with or later than the we low transition, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. each DS3803 has a builtin switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. in a power down condition the voltage on any pin may not exceed the voltage on v cc . 11. t wr1 , t dh1 are measured from we going high. 12. t wr2 , t dh2 are measured from ce going high. dc test conditions outputs open cycle = 200 ns all voltages are referenced to ground ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0 3.0 v timing measurements reference levels: input - 1.5v output - 1.5v input pulse rise and fall times: 5 ns
DS3803 042398 10/10 DS3803 72pin simm module j c d e h g i k l i m f 72 1 a bo p n nv controller side sram and battery side 72pin dim min max a 4.245 4.255 b 3.979 3.989 c 0.845 0.855 d 0.395 0.405 e 0.245 0.255 f 0.050 basic g 0.075 0.085 h 0.245 0.255 i 1.750 basic j 0.120 0.130 k 2.120 2.130 l 2.245 2.255 m 0.057 0.067 n 0.173 o 0.110 p 0.047 0.054
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